1. Field of the Invention
The present invention relates to a shift register apparatus and, more particularly, to a CMOS-based shift register apparatus that consumes less power.
2. Description of the Prior Art
FIG. 1 depicts the construction of a prior art shift register that incorporates CMOSs. In FIG. 1, reference characters Q.sub.P1 -Q.sub.P5 designate P-type field effect transistors (FETs) and Q.sub.N1 -Q.sub.N5 denote N-type FETs.
Each of shift registers SR.sub.1, SR.sub.2, etc. (SR.sub.3 and on omitted from the figure) in different stages comprises a first clocked inverter INV.sub.1 made up of FETs Q.sub.P1, Q.sub.P2, Q.sub.N1 and Q.sub.N2 ; a second clocked inverter INV.sub.2 for latching the output of the clock inverter INV.sub.1 ; and a third inverter INV.sub.3. The second clocked inverter INV.sub.2 contains FETs Q.sub.P3, Q.sub.P4, Q.sub.N3 and Q.sub.N4, while the third clocked inverter INV.sub.3 comprises FETs Q.sub.P5 and Q.sub.N5.
How this prior art shift register works will now be described with reference to FIG. 2. An input signal V.sub.(STRT) supplied to the unit register SR.sub.1 is raised as shown in FIG. 2. When a clock signal VCLK is raised and a complementary clock signal VCLK is lowered at the next timing pulse, the output of the first clocked inverter INV.sub.1 is brought Low. This output is input to the third inverter INV.sub.3.
Thus the output .phi..sub.1 of the first stage unit register SR.sub.1, i.e., the output of the third inverter INV.sub.3, is brought High, which is the same level as that of the input signal V.sub.(STRT).
The output of the third inverter INV.sub.3 is also supplied to the input of the second clocked inverter INV.sub.2. When the clock signal VCLK is inverted, the second clocked inverter INV.sub.2 is activated, latching the output signal .phi..sub.1 in conjunction with the third inverter INV.sub.3.
At this point, the second stage unit register SR.sub.2 reads the output .phi..sub.1 of the first stage unit register SR.sub.1, whereby the output .phi..sub.2 of the second stage unit register SR.sub.2 is brought High.
When the clock signal VCLK is again raised, the already lowered input signal V.sub.(STRT) is read, and the output .phi..sub.1 is brought Low.
With the above process repeated, the input signal V.sub.(STRT) is transferred to the third and fourth stage unit registers SR.sub.3 and SR.sub.4, yielding outputs .phi..sub.3 and .phi..sub.4.
The prior art shift register of the above-described construction is illustratively used in a liquid crystal display (LCD) scanner to generate horizontal sampling pulses. An example of such use will now be described.
In FIG. 3, reference numeral 1 is an input terminal through which a TV video signal is supplied. Past the input signal 1, the video signal is supplied to vertical lines L.sub.1, L.sub.2, . . . L.sub.m through switching elements M.sub.1, M.sub.2, . . . M.sub.m (horizontal switches) each illustratively comprising an N-channel FET. The value "m" represents the number of pixels in the horizontal direction. Furthermore, an m-stage shift register 2 is provided to constitute a horizontal scanning circuit. The shift register 2 is supplied with clock signals .phi..sub.1H and .phi..sub.2H which are "m" times the horizontal frequency. These clock signals consecutively scan driving pulse signals .phi..sub.H1, .phi..sub.H2, . . . .phi..sub.Hm that are output from the output terminals of the shift register 2, the driving pulse signals being supplied to each control terminal of the switching elements M.sub.1 -M.sub.m. Meanwhile, the shift register 2 is supplied with a low potential (V.sub.SS) and a high potential (V.sub.DD). These two kinds of potential are used to generate driving pulses of two potential levels.
Each of the lines L.sub.1 -L.sub.m is connected to one end of each of switching elements M.sub.11, M.sub.21, . . . M.sub.n1, M.sub.12, M.sub.22, . . . M.sub.n2, . . . M.sub.1m, M.sub.2m, . . . M.sub.nm (pixel switches). The value "n" represents the number of horizontal scanning lines. The other end of each of the switching elements M.sub.11 -M.sub.nm is connected to a target terminal 4 via liquid crystal cells C.sub.11, C.sub.21, . . . C.sub.nm.
An n-stage shift register 5 is further provided to constitute a vertical scanning circuit. The shift register 5 is supplied with horizontal frequency clock signals .phi..sub.1v and .phi..sub.2v. These clock signals consecutively scan driving pulse signals .phi..sub.v2, .phi..sub.v2, . . . .phi..sub.vn which are output from output terminals of the shift register 5. The driving pulse signals are supplied to the control terminal representing each horizontal line (M.sub.11 -M.sub.1m), (M.sub.21 -M.sub.2m), . . . (M.sub.n1 -M.sub.nm) of the switching elements M.sub.11 -M.sub.nm making up a matrix 3. Like the shift register 3, the shift register 5 is also supplied with V.sub.SS and V.sub.DD.
In the above circuit, the shift registers 2 and 5 are supplied with clock signals .phi..sub.1H, .phi..sub.2H, .phi..sub.1V and .phi..sub.2V shown in FIGS. 4(A) and 4(B). The shift register 2 outputs signals .phi..sub.H1 -.phi..sub.Hm per pixel cycle, as depicted in FIG. 4(C), and the shift register 5 outputs signals .phi..sub.v1 -.phi..sub.vn per horizontal cycle, as illustrated in FIG. 4 (D). The input terminal 1 is fed with a signal shown in FIG. 4(E).
While the signals .phi..sub.V1 -.phi..sub.H1 are being output, the switching elements M.sub.1, M.sub.11 -M.sub.1m are turned on. This creates a current path comprised of the input terminal 1, M.sub.1, L.sub.1, M.sub.11, C.sub.11 and target terminal 4. The liquid crystal cell C.sub.11 is supplied through this current path with a potential difference between the signal fed to the input terminal 1 and the target terminal 4. Therefore, the cell C.sub.11, within its capacity, samples and holds the charge equivalent to the potential difference caused by the signal of the first pixel. The light transmittance of the liquid crystal is varied depending on the amount of the charge in the cell. The same operation is performed consecutively with the cells C.sub.12 -C.sub.nm. When the signal of the next field is supplied, the amount of the charge in each of the cells C.sub.11 -C.sub.nm is updated.
In this manner, the light transmittance of the liquid crystal cells C.sub.11 -C.sub.nm is varied with respect to each pixel of the video signal. The process is repeated so as to effect TV image displays.
Where the LCD is used, an AC driving scheme is generally utilized for higher reliability and longer service life thereof. In displaying TV images, the video signal is illustratively inverted per field or per frame before being input to the input terminal 1. That is, as shown in FIG. 4(E), the input terminal 1 is supplied with a signal that is inverted per field or per frame.
In the above-described prior art shift register setup, the lines of the clock signals VCLK and VCLK are loaded with the unit registers SR.sub.1 -SR.sub.n in a plurality of stages. This results in a significantly large capacity requirement for the shift register.
As illustrated in FIG. 5, the line of the clock signal VCLK receives the sum of the gate capacities (Q.sub.P3 +Q.sub.N2) of the FETs Q.sub.P3 and Q.sub.N2, and the line of the clock signal VCLK receives the sum of the gate capacities (Q.sub.P1 +Q.sub.N4) of the FETs Q.sub.P1 and Q.sub.N4.
For example, if an MOS transistor gate arrangement measures 7 .mu.m in length and 50 .mu.m in width and if the gate layer thereof is 500 .ANG. thick, the required capacity is 0.49 pF. If the number of shift register stages is 400, the capacity required of each clock line is about 200 pF.
If the output width (A) of a clock signal is 12 volts and the frequency (f) thereof is 3.8 MHz, the power (P) consumed is calculated as follows: EQU P=CA.sup.2 f=200.times.10.sup.-12 .times.144.times.3.8.times.10.sup.6 .apprxeq.109 mW
This means that each clock line consumes 109 mW. Thus one disadvantage of the prior art shift register apparatus is its high power consumption level. Another disadvantage is that a low-impedance large-output clock signal source is needed to drive the prior art shift register apparatus.
More specifically, a liquid crystal view finder containing such shift registers and incorporated for monitoring purposes in a portable TV camera poses an impediment to reducing the power consumption level of the camera as a whole.